A NOVEL CHARGE RECYCLING TECHNIQUE FOR SAVING LEAKAGE POWER IN LOW Vth CMOS CIRCUITS

In this paper, we use an innovative power gating technique to charge recycling the lost energy. We compare conventional circuits and circuit using dual-charge recycling power gating technique in term of the power consumption using the 45 nm Predictive Technology Model. Since we design circuits that it reduces the power consumption of the circuit in the sleep mode, saves energy and costs for the user.
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